Clock skew is a problem in circuit design where signals arrive at different nodes at different time. Clock skew can contribute to 10% of a system cycle time, increased power consumption, and noise. Clock skew is a well-known challenge and its impact may be addressed with clock tree synthesis (CTS) algorithms such as H-tree algorithm, zero skew algorithm, or deferred merge embedding (DME).
A methodical investigation of clock slew, which is the changing rate of voltage through a circuit (or wire) over time, however, is mostly unaddressed. In particular, for clock slew, interconnect resistance significantly increases at every new technology node. The increase in the interconnect resistance makes it more challenging to satisfy slew constraints on long wires. Furthermore, low voltage integrated circuit (IC) design is becoming a norm to limit power density while keeping up with Moore's Law, which exacerbates clock slew.
Current slew-constrained design techniques attempt to fix or avoid timing violations due to slew. Slew-awareness may be part of the clock tree synthesis (i.e. slew-driven).